FII-PRX100 Development Board ( ARTIX 100T, XC7A100T, RISC-V FPGA Developing Board)

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Fraser Innovation Inc develops FII-PRX100 based on the boards of the Xilinx ARTIX-7 series. It was initial released in 2018. This development board is resource-rich and high-speed, making it an ideal platform for learning and engineering research. This development board has been spent a lot on system design, PCB design, and function creation. It could even be said comprehensive and powerful.

System Design Objective

The main purpose of this system design is to complete FPGA learning, development and experiment with Xilin-Vivado. The main device uses the Xilinx-XC7A100T-2FGG676I and is currently the latest generation of FPGA devices from Xilinx. The main learning and development projects can be completed as follows:

1. Basic FPGA design training
2. Construction and training of the SOPC (Microblaze) system
3. IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
4. Development and application based on RISC-V
5. The system is specifically optimized for hardware design for RISC-V system applications

2. System Resource

1. Extended memory
2. Use two Super Srams in parallel to form a 32-bit data interface with a maximum access space of 2M bytes.
3. IS61WV51216 (2 pieces) 512K x 32bit
4. Serial flash
5. Spi interface serial flash (128M bytes)
6. Serial EEPROM
7. Gigabit Ethernet: 100/1000 Mbps
8. USB to serial interface: USB-UART bridge

3. Human-computer Interaction Interface

1. 1. 8 toggle switches
   2. 8 push buttons
   3. Definition of 7 push buttons: up, down, left, right, ok, menu, return
   4. 1 for rest: Reset button
   5. 8 LEDs
   6. 6 7-segment decoders
   7. I2C bus interface
   8. UART external interface
      1. Two JTAG programming interfaces
   9. One is for downloading the FPGA debug interface, and the other one is the JTAG debug interface for the RISC-V CPU
   10. Built-in RISC-V
   11. CPU software debugger, no external RISC-V JTAG emulator required
   12. 12-pin GIPIO connectors, in line with PMOD interface standards

4  Software Development System

1. 1. Vivado 18.1 and later version for FPGA development, Microblaze SOPC
   2. Freedom Studio-Win_x86_64 Software development for RISC-V CPU

5.  Supporting Resources

1. 1. RISC-V JTAG Debugger
   2. xilinx Altera JTAG Download Debugger
   3. FII-PRX100 Development Guide

FII-PRX100 uses Xilinx’s ARTIX-7 series chip, model XC7A100T-2FGG676I, which is currently Xilinx’s latest generation FPGA device.

The Artix-7 is one of the Xilinx 28nn FPGA families. It features a small form factor package that reduces the power consumption of the Artix-7 family by half compared to the Spartan-6 family.

PRX100 system block diagram：

PRX100 Hardware resources：

• It can be powered by external 12V DC source or by “USB Power Supply and Download Interface”. The latter also provides program download functionality. Only one wire is to complete the power supply and download functions;
• A 50 MHz oscillator, a 32.768 kHz oscillator, provides a stable clock source for the development board;
• 6-digit common anode 7-segment decoders, through dynamic scanning to achieve data display;
• 1 HDMI interface displaying color pictures or camera video;
• 1 chip I2C interface EEPROM chip, model AT24C02;
• 1 adaptive 10 M/100M/Gigabit Ethernet interface;
• 8 push buttons, 7 for programmable buttons, 1 for reset button;
• 1 photoresistor, through which it can simulate light control; 1 thermistor, which can collect temperature or analog temperature alarm function; 1 potentiometer, which can simulate voltage change;
• 1 PCF8591 AD/DA conversion chip, reserved external interface, free input and output;
• Onboard 50MHz and 32.768kHz oscillators provide stable clock signals to the development board;
• 8-bit DIP switch;
• 8-bit LED;
• 1 128Mbit Flash chip;
• 4 GPIO external signal expansion interfaces, also the PMOD standard interface;
• A 40-pin GPIO expansion interface that provides a large amount of I/O for developers to use freely;
• Two JTAG interfaces, one for the FPGA download debug interface (J4, J5) and one for the RISC-V CPU JTAG debug interface(J16). Built-in RISC-V CPU software debugger, no external RISC-V JTAG emulator required;
• 1 UART asynchronous serial interface;
• 2 SRAMs with a capacity of 8Mbit;
• a pair of audio input and output interfaces;
• 1 PCIE interface;
• 4 USB interfaces, 2 for the mouse and keyboard interface, 2 for the universal serial interface;
• 1 USB (USB-B) to UART interface for serial communication;
• 1 TFTLCD touch screen interface, which can realize the display and operation of the touch screen;